As semiconductor technology continues to scale, interconnect delay and power consumption threaten to limit the benefits of further scaling. To overcome these bottlenecks, the semiconductor industry is exploring 3D integration through die stacking and through-silicon-vias (TSVs).
A TSV is a metal pillar that connects to a metal layer and is embedded in the device substrate. In a 3D stacked IC (SIC), two or more dies are produced with their own active device and metal layers and then bonded together with vertical TSVs connecting metal layers of adjacent dies. To expose the TSV pillar, much of the substrate is ground away in a process called “thinning” After thinning, metal balls called “microbumps” are added to the end of the TSV for use in bonding.
Because of the move to vertical as opposed to horizontal connections between devices, 3D SICs can lead to a decrease in interconnect length, power consumption, and footprint. To take advantage of these benefits, product quality should be provided at an appropriately high yield. As with any fabricated component, defects may occur during the manufacturing process of die logic and TSVs that can degrade product quality. Therefore, testing schemes are important in order to manufacture reliable chips.
Testing may be carried out before or after dies are assembled onto a stack. Pre-bond testing is directed to detecting defects that are inherent in the manufacture of the internal logic and TSVs, enabling the screening of defective chips and potentially significantly increase stack yield. If a single faulty die is bonded to a stack of otherwise good dies, the whole stack may need to be discarded when a fault is detected during post-bond test. By performing pre-bond testing, it can also be possible to match dies for performance and power.
During pre-bond testing of TSVs, probing can be performed either on the microbumps, the bare TSV pillar, or added probe pads. The thinned wafers are significantly more fragile than standard wafers, so they are generally mounted on a carrier before probing and/or testing with probe cards that apply low contact forces. To inhibit mechanical damage to the microbump or TSV surface, the number of probe touchdowns on the same TSV is limited.
Surface planarity of TSV microbumps impacts not only the quality of connection between a TSV and a probe needle, but also the quality of TSV contacts after bonding. It is therefore desirable not only to planarize microbumps before bonding and TSV test, but also for probes and test methods to be tolerant of non-planarity.
In addition, contacting TSVs with probes prior to bonding can be difficult due to the small pitch and density of TSVs. As an approach to handling the difference in size between current probes and TSVs, previous techniques have introduced large probe pads to TSVs for probe needles. However, large probe pads can limit test access and TSV placement.
Built-in self-test (BIST) techniques have also been proposed for TSV testing and BIST methods for 2D circuits can be extended to pre-bond dies and die logic, but they can require a relatively large amount of die area, and on-chip analog BIST logic is subject to process variations.